Preliminary HLDVT'17 technical program:

Thursday Oct. 5th

08:15-08:30 Prab Varma (Veda Design), Franco Fummi (Università di Verona), Sara Vinco (Politecnico di Torino) Welcoming address

 

Keynote 1
08:30-09:30 Frank Schirrmeister (Cadence Design Systems) Enabling Systems of Systems - Towards Smarter Verification
Session 1: Testing and verification
09:30-10:00 Guy Barash (SanDisk) and Eitan Farchi (IBM Research) A Random Algorithm for Constructing Cross Feature Tests from Single Feature Tests
10:00-10:30 Tonmoy Roy (Virginia Polytechnic Institute and State University) and Michael S Hsiao (Virginia Polytechnic Institute and State University) Reachability Analysis in RTL Circuits Using k-Induction Bounded Model Checking
10:30-11:00 Farzaneh Zokaee (University of Tehran), Hossein Sabaghian-Bidgoli (University of Kashan), Vahid Janfaza (University of Tehran), Payman Behnam (University of Tehran) and Zainalabedin Navabi (University of Tehran) A Novel SAT-based ATPG Approach for Transition Delay Faults
11:00-11:30 Coffee break
Embedded tutorial 1
11:30-12:30 Fei Xie (Portland State University) Hardware/Firmware/Software Co-validation for Secure Systems-on-Chips
12:30-01:30 Lunch
Keynote 2
01:30-02:30 Rainer Doemer (University of California) Attacking the System Validation Challenge with Advanced Parallel Simulation: The Good News and the Bad News
Special session: Quantum computing
02:30-03:15 Yehuda Naveh (IBM) Quantum computing: An introduction, a status check, and challenges in verification
03:15-4:00 Kevin O'Brien (University of California at Berkeley), Vinay Ramasesh (University of California at Berkeley), William Livingston (University of California at Berkeley), Allison Dove (University of California at Berkeley), James Colless (University of California at Berkeley), John Mark Kreikebaum (University of California at Berkeley) and Irfan Siddiqi (University of California at Berkeley) Design, characterization and simultaneous multiplexed readout of a multi-qubit processor
04:00-04:30 Coffee break
Session 2: Modeling and validation
04:30-05:00 Michele Lora (University of Verona) Validation of HMI Applications for Industrial Smart Display
05:00-04:30 Maral Amir (University of California) and Tony Givargis (University of California) HES Machine: Harmonic Equivalent State Machine Modeling for Cyber-Physical Systems
05:30-6:00 Sophia Balkovski (University of California) and Ian Harris (University of California) Designing Cyber-Physical Systems from Natural Language Descriptions

 

Friday Oct. 6th

Keynote 3
08:30-09:30 Tajana Šimunić Rosing (University of California) Reliability and maintainability of IoT systems
Session 3: Post-silicon validation and 3D design
09:30-10:00 Pankaj Moharikar (Infineon Technologies) and Jayakrishna Guddeti (Infineon Technologies) Automated test generation for post silicon microcontroller validation
10:00-10:30 Siroos Madani (University of Louisiana), Kasem Khalil (University of Louisiana), Bappaditya Dey (University of Louisiana), Devante Bonton (University of Louisiana) and Magdy Bayoumi (University of Louisiana) Repair Techniques for Aged TSVs in 3D Integrated Circuits
10:30-11:00 Binod Kumar (IIT Bombay), Kanad Basu (Synopsys), Masahiro Fujita (University of Tokyo) and Virendra Singh (IIT Bombay) RTL level trace signal selection and coverage estimation during post-silicon validation
11:00-11:30 Coffee break
Embedded tutorial 2
11:30-12:30 Pierluigi Nuzzo (University of Southern California) Building Correct Industrial Cyber-Physical Systems: Formal Foundations, Methodology, and Tools
12:30-01:30 Lunch
Session 4: Applied design and verification techniques
01:30-02:00 Florenc Demrozi (University of Verona), Riccardo Zucchelli (University of Verona) and Graziano Pravadelli (University of Verona) Exploiting Sub-Graph Isomorphism and Probabilistic Neural Networks for the Detection of Hardware Trojans at RTL
02:00-02:30 Zhongqi Cheng (University of California), Tim Schmidt (University of California), Guantao Liu (University of California) and Rainer Doemer (University of California) Thread- and Data-Level Parallel Simulation of a Bitcoin Miner Model in SystemC
02:30-03:00 Daniela De Venuto (Politecnico di Bari), Giovanni Mezzina (Politecnico di Bari) and Vito Leonardo Gallo (Politecnico di Bari) Design and Implementation of FPGA-based Muscle Conduction Velocity Tracker in Dynamic Contractions during the Gait
03:00-03:30 Coffee break
WiP session
03:30-03:50 Zahra Shirmohammadi (Shahid Rajaee University), Hadi Zamani Sabzi (University of California) and Seyed Ghassem Miremadi (Sharif University) 3D-DyCAC: Dynamic Numerical-Based Mechanism for Reducing Crosstalk Faults in 3D ICs
03:50-04:10 Masahiro Fujita (University of Tokyo) An approach to approximate computing: Logic transformations for one-minterm changes in specification
04:10-04:30 Keerthikumara Devarajegowda  (Infineon Technologies) and Wolfgang Ecker (Infineon Technologies) On Generation of Properties from Specification
04:30 Closing session